1. Field of the Invention
The present invention is related to an Electro-Static Discharge (ESD) circuit, and more particularly to an ESD circuit comprising active guard ring structure which is applicable to improving latch-up immunity under I-test.
2. Description of the Prior Art
Parastic PNPN paths are often existing in chips. It is needed to be aware of related short circuit failure identified as “Latch-up” for IC designers in both development and layout stages. Such failure brings out huge abnormal current from supply to ground if unexpected conduction through the parasitic PNPN structure is generated after voltage/current fluctuation is triggered at I/O pads. Therefore, to examine the latch-up immunity, methods as positive and negative I-test are defined in JEDEC standards (1997). In certain standards, a positive or negative trigger current valued 100 mA is injected in an I/O pin of the CMOS IC so as to examine if the latch-up occurs. Below is Table I provided, which shows the specification of the JEDEC standards, and has been widely used for decades by many companies to examine if their product ICs can pass the latch-up test.
TABLE ITrigger SourceSpecificationPositive current at I/O pinInorm + 100 mA (or 1.5 * Inorm)Negative current at I/O pin−100 mA (or −0.5 * Inorm)Over-Voltage at VDD pin1.5 * VDD-Max
When it comes to 2011, the JEDEC standards (1997) has been updated to JESD78D (Nov. 2011), in which the trigger current of the highest latch-up level has been pursued to increasing from the previous +/−100 mA to +/−200 mA. Accordingly, for many companies, to promote and to examine the IC products to over 200 mA robustness against latch-up becomes a target specification. Since all the developments and layout stages for latch-up immunity were built under the previous specifications having trigger current equals +/−100 mA, when it is updated to +/−200 mA, methods as additional guard rings are proposed and implemented in the products so as to meet the latest standards. Nevertheless, by disposing additional guard rings in the products, it is merely designed for absorbing electrons or holes dissipating in the substrate/well of the IC and is known as such typical kind of passive strategy to increase the latch-up resistance of the chip.
Meanwhile, it is highly emphasized that methods as disposing additional guard rings are only effective upon those areas where the guard rings are located. In other words, for other areas where no guard rings are disposed, its latch-up immunity cannot be improved by doing so.
Moreover, when employing the traditional strategy to increase latch-up immunity, the tolerance toward the trigger current is always related to width of the guard ring and the distance to the internal latch-up paths. As such, when the I-test defined in JEDEC standards is updated from +/−100 mA to +/−200 mA, not only width and contacts of the guard ring, but also the distance from the I/O cells to the internal latch-up circuit must be increased. A plurality of design rules also have to be updated and modified to meet the new standards JESD78D. As a result, fabrication cost and production complexity will thus be affected and highly increased as well.
On account of all, it should be obvious that there is indeed an urgent need for the professionals in the field for a new active guard ring structure to be developed that can actively and aggressively improve latch-up immunity of IC design so as to solve the above-mentioned problems occurring in the prior design.